1. Customizable, domain optimized RISCV-based FPGA Overlays

Team Members: Shreenithi Iyer, Hrishikesh Nair, Aditya Jain and Ashuthosh M. R.

This project has been funded by Semiconductor Research Corporation


With the deceleration of Moore’s law and Dennard scaling, general-purpose compute architectures will need to be complemented by domain-specific acceleration for significant performance improvement. Deploying several different hardened application-specific accelerators (such as the Google TPU)presents datacenter scale provisioning and orchestration challenges.

Other more general-purpose programmable compute engines such as CPUs and GPUs are not specialized for the workload at hand and are therefore inherently inefficient. FPGAs are a potent, flexible acceleration architecture that is intrinsically capable of adapting to very different workloads. However, leveraging FPGAs as accelerator comes with its own challenges that require specialized skills and hinder programmer productivity.


1. Customizable, domain optimized RISCV-based FPGA Overlays