5. Sub-Threshold Standard Cell Design

Team members: Karthik, Vinay, Vikram Kannur, Ishita Agarwal and Kaushika

In the present era of high-density and high-speed nanoelectronics, power consumption has been one of the most concerning factors.  Hence there is a rapidly growing demand for ultra-low power devices and advanced energy-saving methods for digital integrated circuits. The need for low-power circuits has up to now been limited to a small number of products, but this situation has changed drastically in the last few years, primarily because of the growing need for portability in computing and telecommunication products.

We further reduce the energy consumption of the commercial UMC 28nm High-Performance Compact CMOS Process Technology by down-scaling the supply voltage. We verify an 8-bit ALU consuming 41.9 uW with X1 standard cells as opposed to the 1.29 mW with regular cells. We verify a 2-stage RISC-V-v2 processor with and without branch predictors at 5MHz, 10MHz, 20MHz. We reduce the power consumption by up to 30.78 times with the ALU and are able to achieve a better quality of results upon using the optimization algorithms.

We automate significant parts of the logic gate design process, enabling the rapid adoption of new processes or alternative designs.

5. Sub-Threshold Standard Cell Design