The Azurite core generator at InCore today houses a wide variety of configurable features. In this project, we take a few standard configurations (architectural and micro-architectural) of Azurite and perform synthesis using OpenLane and Commercial Tools. This will provide an initial estimate of PPA and indicate opportunities to enhance the core for either performance, area, and/or Power.

The outputs also include building a complete automated flow (using OpenLane and Commercial flows) which can be incorporated in a CI and thereby enable quick comparison with older versions of the core.

A separate aspect of this exercise also includes building a script that will allow the azurite instance generated to be treated as a Vivado board-design IP. This will allow customers to readily use this IP to build their own custom SoCs using 3rd party IPs.

Instruction Profiler - RISC-V Profiling for identification of custom instruction-set extensions