RISC-V Profiling for identification of custom instruction-set extension RISC V is rapidly making its place in almost all domains with its ability to improve the performance and efficiency of a program. In processor design, the instruction set architecture is mainly decided based on the requirements of the application. An extendable ISA lets the user make application-specific adjustments for improved performance at the cost of additional area and more complex design. Adding a custom instruction also lets one decide whether to use additional hardware or existing ones with embedded software. To enable and disable the instructions we used Codasip Studio 9.2.0, under the instruction accurate (IA) model with O3 optimization for ease of integrability.

After comparing the results of cycle count and the area utilized from Codasip studio for the Embench benchmarks considered we conclude that the instructions can be implemented as full hardware or full software or hybrid model. It was observed that a maximum of 42.131% cycle improvement and a maximum of 1.198% area reduction was possible by using the optimal solution for the Embench benchmarks.