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Sub-Threshold Standard Cell Design

Team Members: Vardhan, Yagna Vivek, Sashank Sharma, Ishitha Aagarwal, Vikram Kannur

In the present era of high-density and high-speed nanoelectronics, power consumption has been one of the most concerning factors. Hence there is a rapidly growing demand for ultra-low power devices and advanced energy-saving methods for digital integrated circuits. The need for low-power circuits has up to now been limited to a small number of products, but this situation has changed drastically in the last few years, mainly because of the growing need for portability in computer and telecommunication products.

In this work, we discuss the motivation, trends, and challenges of operating digital circuits in the sub-threshold regime using UMC’s commercial 0.18 𝜇m and 28nm high-performance compact high-K bulk CMOS processes. We synthesize a 32-bit 6-pipeline stage RV32IMFC Chromite RISC-V core, PULP, and PicoRV32 RISC-V cores. We further reduce the energy consumption of the commercial UMC 55nm High-Performance Compact CMOS Process Technology by down-scaling the supply voltage.

We automate significant parts of the logic gate design process, enabling the rapid adoption of new processes or alternative designs.

Sub-Threshold Standard Cell Design
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